1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to a semiconductor memory device operating in synchronization with an external clock.
2. Description of the Background Art
In the field of data processing for example, system LSI (Large Scale Integrated Circuit) has recently been in wide use. The system LSI has a memory device and a logic device such as microprocessor that are integrated on the same semiconductor chip for the purpose of achieving fast data processing with low power consumption. This system LSI has the following advantages as compared with the conventional system having individual memory and logic devices soldered onto a printed circuit board.
(1) The load on a signal line is smaller than that on the interconnection on the printed circuit board and thus fast data-signal-transmission is possible.
(2) There is no restriction on the number of pin terminals of the memory device and thus a data bus with a greater width can be provided between the memory device and the logic device to increase the data transfer rate.
(3) Components of the system LSI are integrated on the system LSI chip while the conventional configuration has individual components separately mounted on the printed circuit board, and thus the system LSI can be made compact and lightweight.
(4) Circuits having respective functions are arranged on the system LSI chip and thus the design efficiency is improved.
The system LSI which is advantageous as discussed above is accordingly in wide use in several fields. Examples of the memory device integrated in the system LSI are DRAM (Dynamic Random-Access Memory), SRAM (Static Random-Access Memory) and flash EEPROM (Electrically Erasable and Programmable Read-Only Memory). Examples of the integrated logic device of the system LSI are processor for control and processing and logic circuit such as A/D (Analog-to-Digital) conversion circuit for analog processing and dedicated logic processing.
Among the examples of the integrated memory device on the system LSI, DRAM is generally employed that achieves a greater capacity while keeping the same degree of integration as that of other memory devices.
FIG. 37 is a circuit diagram showing a configuration of a data read circuit 200 of separate IO type that is integrated in a DRAM.
Referring to FIG. 37, data read circuit 200 includes bit lines BL and /BL, read data lines /IOR and IOR, a bit line precharge/equalize circuit P/E, and a read gate RG electrically connecting read data lines /IOR and IOR each to a ground voltage GND in response to a signal on a read column selection line CSLR and the voltage level on bit lines BL and /BL. Here, binary states of signals and signal lines, i.e., high voltage state (power supply voltage Vcc) and low voltage state (ground voltage GND) are respectively referred to as xe2x80x9cH levelxe2x80x9d and xe2x80x9cL level.xe2x80x9d
Bit line precharge/equalize circuit P/E precharges/equalizes bit lines BL and /BL to an intermediate voltage VBL (Vcc/2) during an H-level period of a bit line equalize signal BLEQ.
Read gate RG includes N-channel MOS transistors TGc and TGe connected in series between read data line /IOR and ground voltage GND and N-channel MOS transistors TGd and TGf connected in series between read data line IOR and ground voltage GND.
N-channel MOS transistors TGe and TGf have respective gates connected to bit lines BL and /BL respectively. To respective gates of N-channel MOS transistors TGc and TGd, the signal on read column selection line CSLR is supplied.
Data read circuit 200 further includes a sense amplifier circuit SA amplifying a slight potential difference between bit lines BL and /BL, a preamplifier PA amplifying a slight potential difference between read data lines /IOR and IOR, and a read data line precharge/equalize circuit EQ.
Read data line precharge/equalize circuit EQ precharges/equalizes read data lines /IOR and IOR to power supply voltage Vcc during an L-level period of a read data line equalize signal /IOREQ.
In data read circuit 200, bit lines BL and /BL are precharged to the intermediate voltage VBL and read data lines /IOR and IOR are precharged to the power supply voltage Vcc even in a standby state and a self-refresh state in which no data is read from a desired memory cell (hereinafter also referred to as selected memory cell). Then, even if the signal on read column selection line CSLR has L level, respective drains of N-channel MOS transistors TGc and TGd are set at power supply voltage Vcc and respective sources of N-channel MOS transistors TGc and TGd are set at ground voltage GND. Accordingly, off leakage current flows between the drain and source of N-channel MOS transistors TGc and TGd each.
A technique of decreasing such an off leakage current of the transistors thereby reducing power consumption in a standby or self-refresh state of the DRAM is disclosed for example in Japanese Patent Laying-Open No. 8-203268, pp. 10-14 (hereinafter referred to as conventional art). This conventional art, however, cannot completely prevent the off leakage current from flowing.
For the above-discussed reason, the off leakage current of the transistors generally flows in the DRAM in a standby or self-refresh state. In particular, the system LSI having the integrated DRAM as a memory device generally includes several hundreds of IO lines. Accordingly, a greater off leakage current flows through the IO lines and thus it is likely that the power consumption in the standby or self-refresh state increases.
One object of the present invention is to provide a semiconductor memory device completely shutting off the off leakage current in the transistor provided between the data line and the bit line in a predetermined period in which no data access is executed and accordingly reducing power consumption.
In summary, according to one aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a first data line electrically connected to selected one of the memory cells in response to activation of a word line, a second data line hierarchically provided with respect to the first data line, a read circuit provided between the first data line and the second data line to drive the second data line to a fixed voltage with a driving power according to a voltage on the first data line at the time of data reading, and a voltage supply control circuit for supplying a predetermined voltage to the second data line in response to a precharge/equalize instruction. The voltage supply control circuit includes a voltage supply stop circuit disconnecting the second data line from the predetermined voltage in a predetermined period except for the time of data reading.
According to another aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a first data line electrically connected to selected one of the memory cells in response to activation of a word line, a second data line hierarchically provided with respect to the first data line, a switch circuit provided between the first data line and the second data line to electrically connect the first data line and the second data line at the time of data access, and a voltage supply control circuit for supplying a predetermined voltage to the second data line in response to a precharge/equalize instruction. The voltage supply control circuit includes a voltage supply stop circuit disconnecting the second data line from the predetermined voltage in a predetermined period except for the time of data access.
A chief advantage of the present invention is that a semiconductor memory device is achieved with the power consumption reduced by completely shutting off the off leakage current in the transistor provided between the first and second data lines in a predetermined period in which no data access is carried out.
According to still another aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a plurality of first data lines, a plurality of second data lines hierarchically provided with respect to the first data lines respectively, a plurality of read circuits respectively provided between the first data lines and the second data lines to drive the second data lines corresponding respectively to the first data lines to a fixed voltage with a driving power according to respective voltages on the plurality of first data lines at the time of data reading, a power supply node supplying a predetermined voltage, a voltage supply line, a voltage supply stop circuit provided between said power supply node and said voltage supply line to electrically connect said power supply node and said voltage supply line at the time of data reading, and a plurality of voltage supply control circuits provided correspondingly to the second data lines respectively for electrically connecting the voltage supply line and the second data lines in response to a precharge/equalize instruction, the voltage supply stop circuit disconnecting the power supply node from the voltage supply line in a predetermined period except for the time of data reading. Selected one of the first data lines is electrically connected to selected one of the memory cells in response to activation of a word line.
Another advantage of the present invention is that a semiconductor memory device is achieved with the power consumption reduced by controlling supply of the voltage from one power supply node to a plurality of voltage supply control circuits.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.